Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits
نویسندگان
چکیده
We demonstrate a novel algorithm for assigning the threshold voltage to the gates in a digital random logic complementary metal—oxide—semiconductor (CMOS) circuit for a dual-threshold voltage process. The tradeoff between static and dynamic power consumption has been explored. When used along with device sizing and supply voltage reduction techniques for low power, the proposed algorithm can reduce the total power dissipation of a circuit by as much as 50%.
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ورودعنوان ژورنال:
- IEEE Trans. VLSI Syst.
دوره 9 شماره
صفحات -
تاریخ انتشار 2001